The L0 caches on the compute units is now increased numerically by 240%. 'Navi 31' hence has a total Infinity Cache size of 96 MB-which may be less in comparison to the 128 MB on 'Navi 21,' but AMD has shored up cache sizes across the GPU. In the scheme of things, the GPU has a contiguous and monolithic 384-bit wide memory bus, because every modern GPU uses multiple on-die memory controllers to achieve a wide memory bus. Six of these add up to the GPU's 384-bit GDDR6 memory interface. Custom interconnects tie it with the six MCDs.Įach MCD has 16 MB of Infinity Cache (元 cache) and a 64-bit GDDR6 memory interface (two 32-bit GDDR6 paths).
It features the latest-generation multimedia engine with dual-stream encoders and the new Radiance display engine with DisplayPort 2.1 and HDMI 2.1a support. The GCD interfaces with the system over a PCI-Express 4.0 x16 host interface. The slide details the 'Navi 31' MCM, with its central graphics compute die (GCD) chiplet that's built on the 5 nm EUV silicon fabrication process, surrounded by six memory cache dies (MCDs), each built on the 6 nm process. An alleged leaked company slide details AMD's upcoming 5 nm 'Navi 31' GPU powering the next-generation Radeon RX 7900 XTX and RX 7900 XT graphics cards.
